Estimating a Cost of Implementing an Operation Unit Graph on a Reconfigurable Processor

ABSTRACT

A cost estimation tool in a system for implementing an operation unit graph on a reconfigurable processor is presented as well as a method of operating a cost estimation tool for estimating a cost of implementing an operation unit graph. The operation unit graph may include first and second logical units that perform first and second data operations and have first and second ports, respectively, coupled by a logical edge, on a reconfigurable processor. The method includes receiving the operation unit graph, determining first and second upper bandwidth limits of the first and second ports, respectively, determining a logical edge bandwidth of the logical edge based on the first and second upper bandwidth limits, determining a timing group for the logical edge, and providing the logical edge bandwidth and the timing group as a cost estimation of implementing the operation unit graph on the reconfigurable processor.

RELATED APPLICATIONS AND DOCUMENTS

This application claims the benefit of U.S. Provisional Patent Application No. 63/388,915, entitled, “Cost Model: Each graph annotated with bandwidth requirements; cost minimization over the graph” filed on 13 Jul. 2022. The provisional application is hereby incorporated by reference for all purposes.

This application also is related to the following papers and commonly owned applications:

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No. 11,323,124 B1, filed Jun. 3, 2021, entitled         “VARIABLE-LENGTH CLOCK STRETCHER WITH CORRECTION FOR GLITCHES         DUE TO FINITE DLL BANDWIDTH;”     -   U.S. Nonprovisional patent application Ser. No. 17/338,625, now         U.S. Pat. No. 11,239,846 B1, filed Jun. 3, 2021, entitled         “VARIABLE-LENGTH CLOCK STRETCHER WITH CORRECTION FOR GLITCHES         DUE TO PHASE DETECTOR OFFSET;”     -   U.S. Nonprovisional patent application Ser. No. 17/338,626, now         U.S. Pat. No. 11,290,113 B1, filed Jun. 3, 2021, entitled         “VARIABLE-LENGTH CLOCK STRETCHER WITH CORRECTION FOR DIGITAL DLL         GLITCHES;”     -   U.S. Nonprovisional patent application Ser. No. 17/338,629, now         U.S. Pat. No. 11,290,114 B1, filed Jun. 3, 2021, entitled         “VARIABLE-LENGTH CLOCK STRETCHER WITH PASSIVE MODE JITTER         REDUCTION;”     -   U.S. Nonprovisional patent application Ser. No. 17/405,913, now         U.S. Pat. No. 11,334,109 B1, filed Aug. 18, 2021, entitled         “VARIABLE-LENGTH CLOCK STRETCHER WITH COMBINER TIMING LOGIC;”     -   U.S. Provisional Patent Application No. 63/230,782, filed Aug.         8, 2021, entitled “LOW-LATENCY MASTER-SLAVE CLOCKED STORAGE         ELEMENT;”     -   U.S. Provisional Patent Application No. 63/236,218, filed Aug.         23, 2021, entitled “SWITCH FOR A RECONFIGURABLE DATAFLOW         PROCESSOR;”     -   U.S. Provisional Patent Application No. 63/236,214, filed Aug.         23, 2021, entitled “SPARSE MATRIX MULTIPLIER;”     -   U.S. Provisional Patent Application No. 63/389,767, filed Jul.         15, 2022. entitled “PEER-TO-PEER COMMUNICATION BETWEEN         RECONFIGURABLE DATAFLOW UNITS;”     -   U.S. Provisional Patent Application No. 63/405,240, filed Sep.         9, 2022, entitled “PEER-TO-PEER ROUTE THROUGH IN A         RECONFIGURABLE COMPUTING SYSTEM.”         All of the related application(s) and documents listed above are         hereby incorporated by reference herein for all purposes.

FIELD OF THE TECHNOLOGY DISCLOSED

The present technology relates to a cost estimation tool, and more particularly, to method of operating a cost estimation tool for estimating a cost of implementing an operation unit graph on a reconfigurable processor, to a system for implementing an operation unit graph on a reconfigurable processor that comprises a cost estimation tool, and to a non-transitory computer-readable storage medium including instructions that, when executed by a processing unit, cause the processing unit to operate a cost estimation tool for estimating a cost of implementing an operation unit graph on a reconfigurable processor.

BACKGROUND

The subject matter discussed in this section should not be assumed to be prior art merely as a result of its mention in this section. Similarly, a problem mentioned in this section or associated with the subject matter provided as background should not be assumed to have been previously recognized in the prior art. The subject matter in this section merely represents different approaches, which in and of themselves can also correspond to implementations of the claimed technology.

Reconfigurable processors, including FPGAs, can be configured to implement a variety of functions more efficiently or faster than might be achieved using a general-purpose processor executing a computer program. So-called coarse-grained reconfigurable architectures (CGRAs) are being developed in which the configurable units in the array are more complex than used in typical, more fine-grained FPGAs, and may enable faster or more efficient execution of various classes of functions. For example, CGRAs have been proposed that can enable implementation of low-latency and energy-efficient accelerators for machine learning and artificial intelligence workloads.

With the rapid expansion of applications that can be characterized by dataflow processing, such as natural-language processing and recommendation engines, the performance and efficiency challenges of traditional, instruction set architectures have become apparent. First, the sizable, generation-to-generation performance gains for multicore processors have tapered off. As a result, developers can no longer depend on traditional performance improvements to power more complex and sophisticated applications. This holds true for both CPU fat-core and GPU thin-core architectures.

A new approach is required to extract more useful work from current semiconductor technologies. Amplifying the gap between required and available computing is the explosion in the use of deep learning. According to a study by OpenAI, during the period between 2012 and 2020, the compute power used for notable artificial intelligence achievements has doubled every 3.4 months.

It is common for GPUs to be used for training and CPUs to be used for inference in machine learning systems based on their different characteristics. Many real-life systems demonstrate continual and sometimes unpredictable change, which means predictive accuracy of models declines without frequent updates.

Finally, while the performance challenges are acute for machine learning, other workloads such as analytics, scientific applications and even SQL data processing all could benefit from dataflow processing. New approaches should be flexible enough to support broader workloads and facilitate the convergence of machine learning and high-performance computing or machine learning and business applications.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, like reference characters generally refer to like parts throughout the different views. Also, the drawings are not necessarily to scale, with an emphasis instead generally being placed upon illustrating the principles of the technology disclosed. In the following description, various implementations of the technology disclosed are described with reference to the following drawings.

FIG. 1 is a diagram of an illustrative data processing system including a coarse-grained reconfigurable (CGR) processor, CGR processor memory, and a host processor.

FIG. 2 is a diagram of an illustrative computer, including an input device, a processor, a storage device, and an output device.

FIG. 3 is a diagram of an illustrative reconfigurable processor including a top-level network (TLN) and two CGR arrays.

FIG. 4 is a diagram of an illustrative CGR array including CGR units and an array-level network (ALN).

FIG. 5 illustrates an example of a pattern memory unit (PMU) and a pattern compute unit (PCU), which may be combined in a fused-control memory unit (FCMU).

FIG. 6 is a diagram of an illustrative compiler stack implementation suitable for generating a configuration file for a reconfigurable processor.

FIG. 7 is a diagram of an illustrative operation unit graph.

FIG. 8 is a diagram of an illustrative cost estimation tool that receives an operation unit graph and provides logical edge bandwidths and timing groups of logical edges as a cost estimation of implementing the operation unit graph on a reconfigurable processor.

FIG. 9 is a flowchart showing illustrative operations that a cost estimation tool performs for estimating a cost of implementing an operation unit graph on a reconfigurable processor.

DETAILED DESCRIPTION

The following discussion is presented to enable any person skilled in the art to make and use the technology disclosed and is provided in the context of a particular application and its requirements. Various modifications to the disclosed implementations will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other implementations and applications without departing from the spirit and scope of the technology disclosed. Thus, the technology disclosed is not intended to be limited to the implementations shown but is to be accorded the widest scope consistent with the principles and features disclosed herein.

Traditional compilers translate human-readable computer source code into machine code that can be executed on a Von Neumann computer architecture. In this architecture, a processor serially executes instructions in one or more threads of software code. The architecture is static and the compiler does not determine how execution of the instructions is pipelined, or which processor or memory takes care of which thread. Thread execution is asynchronous, and safe exchange of data between parallel threads is not supported.

Applications for machine learning (ML) and artificial intelligence (AI) may require massively parallel computations, where many parallel and interdependent threads (metapipelines) exchange data. Therefore, such applications are ill-suited for execution on Von Neumann computers. They require architectures that are adapted for parallel processing, such as coarse-grained reconfigurable (CGR) architectures (CGRAs) or graphic processing units (GPUs).

The ascent of ML, AI, and massively parallel architectures places new requirements on compilers. Reconfigurable processors, and especially CGRAs, often include specialized hardware elements such as compute units and memory units that operate in conjunction with one or more software elements such as a host processor and attached host memory, and are particularly efficient for implementing and executing highly-parallel applications such as machine learning applications.

Thus, such compilers are required to pipeline computation graphs, or dataflow graphs, decide which operations of an operation unit graph are assigned to which portions of the reconfigurable processor, how data is routed between various compute units and memory units, and how synchronization is controlled, particularly when a dataflow graph includes one or more nested loops, whose execution time varies dependent on the data being processed.

In this context, it is particularly important for the compiler to perform hardware resource allocation during placement and routing such that the performance of a dataflow graph implementation on a given reconfigurable processor is maximized while the implementation optimizes the utilization rate of the reconfigurable processor's hardware resources.

Therefore, it is desirable to provide a new cost estimation tool and a method of operation such a cost estimation tool that is particularly suited for guiding the compiler during the compilation of highly-parallel applications for achieving a high-performance implementation of the highly-parallel applications on a given reconfigurable processor. The new cost estimation tool should provide an accurate estimation of the actual cost of implementing an application on the given reconfigurable processor. The new cost estimation tool should further use few compute resources and be able to provide such an accurate estimation in a short period of time.

FIG. 1 illustrates an example data processing system 100 including a host processor 180, a reconfigurable processor such as a coarse-grained reconfigurable (CGR) processor 110, and an attached CGR processor memory 190. As shown, CGR processor 110 has a coarse-grained reconfigurable architecture (CGRA) and includes an array of CGR units 120 such as a CGR array. CGR processor 110 may include an input-output (I/O) interface 138 and a memory interface 139. Array of CGR units 120 may be coupled with (I/O) interface 138 and memory interface 139 via databus 130 which may be part of a top-level network (TLN). Host processor 180 communicates with I/O interface 138 via system databus 185, which may be a local bus as described hereinafter, and memory interface 139 communicates with attached CGR processor memory 190 via memory bus 195.

Array of CGR units 120 may further include compute units and memory units that are interconnected with an array-level network (ALN) to provide the circuitry for execution of a computation graph or a data flow graph that may have been derived from a high-level program with user algorithms and functions. A high-level program is source code written in programming languages like Spatial, Python, C++, and C. The high-level program and referenced libraries can implement computing structures and algorithms of machine learning models like AlexNet, VGG Net, GoogleNet, ResNet, ResNeXt, RCNN, YOLO, SqueezeNet, SegNet, GAN, BERT, ELMo, USE, Transformer, and Transformer-XL.

If desired, the high-level program may include a set of procedures, such as learning or inferencing in an AI or ML system. More specifically, the high-level program may include applications, graphs, application graphs, user applications, computation graphs, control flow graphs, data flow graphs, models, deep learning applications, deep learning neural networks, programs, program images, jobs, tasks and/or any other procedures and functions that may perform serial and/or parallel processing.

The architecture, configurability, and data flow capabilities of CGR array 120 enables increased compute power that supports both parallel and pipelined computation. CGR processor 110, which includes CGR arrays 120, can be programmed to simultaneously execute multiple independent and interdependent data flow graphs. To enable simultaneous execution, the data flow graphs may be distilled from a high-level program and translated to a configuration file for the CGR processor 110. In some implementations, execution of the data flow graphs may involve using more than one CGR processor 110.

Host processor 180 may be, or include, a computer such as further described with reference to FIG. 2 . Host processor 180 runs runtime processes 170, as further referenced herein. In some implementations, host processor 180 may also be used to run computer programs, such as the compiler 160 further described herein with reference to FIG. 6 . In some implementations, the compiler may run on a computer that is similar to the computer described with reference to FIG. 2 , but separate from host processor 180.

The compiler may perform the translation of high-level programs to executable bit files. While traditional compilers sequentially map operations to processor instructions, typically without regard to pipeline utilization and duration (a task usually handled by the hardware), an array of CGR units 120 requires mapping operations to processor instructions in both space (for parallelism) and time (for synchronization of interdependent computation graphs or data flow graphs). This requirement implies that a compiler for the CGR array 120 decides which operation of a computation graph or data flow graph is assigned to which of the CGR units in the CGR array 120, and how both data and, related to the support of data flow graphs, control information flows among CGR units, and to and from host processor 180 and attached CGR processor memory 190.

CGR processor 110 may accomplish computational tasks by executing a configuration file (e.g., a processor-executable format (PEF) file). For the purposes of this description, a configuration file corresponds to a data flow graph, or a translation of a data flow graph, and may further include initialization data. A compiler compiles the high-level program to provide the configuration file 165. Runtime processes 170 may install the configuration file 165 in CGR processor 110. In some implementations described herein, a CGR array 120 is configured by programming one or more configuration stores with all or parts of the configuration file 165. Therefore, the configuration file is sometimes also referred to as a programming file.

A single configuration store may be at the level of the CGR processor 110 or the CGR array 120, or a CGR unit may include an individual configuration store. The configuration file 165 may include configuration data for the CGR array and CGR units in the CGR array, and link the computation graph to the CGR array 120. Execution of the configuration file by CGR processor 110 causes the CGR array (s) to implement the user algorithms and functions in the data flow graph.

CGR processor 110 can be implemented on a single integrated circuit (IC) die or on a multichip module (MCM). An IC can be packaged in a single chip module or a multichip module. An MCM is an electronic package that may comprise multiple IC dies and other devices, assembled into a single module as if it were a single device. The various dies of an MCM may be mounted on a substrate, and the bare dies of the substrate are electrically coupled to the surface or to each other using for some examples, wire bonding, tape bonding or flip-chip bonding.

FIG. 2 illustrates an example of a computer 200, including an input device 210, a processor 220, a storage device 230, and an output device 240. Although the example computer 200 is drawn with a single processor 220, other implementations may have multiple processors. Input device 210 may comprise a mouse, a keyboard, a sensor, an input port (e.g., a universal serial bus (USB) port), and/or any other input device known in the art. Output device 240 may comprise a monitor, printer, and/or any other output device known in the art. Illustratively, part or all of input device 210 and output device 240 may be combined in a network interface, such as a Peripheral Component Interconnect Express (PCIe) interface suitable for communicating with CGR processor 110 of FIG. 1 .

Input device 210 is coupled with processor 220, which is sometimes also referred to as host processor 220, to provide input data. If desired, memory 226 of processor 220 may store the input data. Processor 220 is coupled with output device 240. In some implementations, memory 226 may provide output data to output device 240.

Processor 220 further includes control logic 222 and arithmetic logic unit (ALU) 224. Control logic 222 may be operable to control memory 226 and ALU 224. If desired, control logic 222 may be operable to receive program and configuration data from memory 226. Illustratively, control logic 222 may control exchange of data between memory 226 and storage device 230. Memory 226 may comprise memory with fast access, such as static random-access memory (SRAM). Storage device 230 may comprise memory with slow access, such as dynamic random-access memory (DRAM), flash memory, magnetic disks, optical disks, and/or any other memory type known in the art. At least a part of the memory in storage device 230 includes a non-transitory computer-readable medium (CRM) 235, such as used for storing computer programs. The storage device 230 is sometimes also referred to as host memory.

FIG. 3 illustrates example details of a CGR architecture 300 including a top-level network (TLN 330) and two CGR arrays (CGR array 310 and CGR array 320). A CGR array comprises an array of CGR units (e.g., pattern memory units (PMUs), pattern compute units (PCUs), fused-control memory units (FCMUs)) coupled via an array-level network (ALN), e.g., a bus system. The ALN may be coupled with the TLN 330 through several Address Generation and Coalescing Units (AGCUs), and consequently with input/output (I/O) interface 338 (or any number of interfaces) and memory interface 339. Other implementations may use different bus or communication architectures.

Circuits on the TLN in this example include one or more external I/O interfaces, including I/O interface 338 and memory interface 339. The interfaces to external devices include circuits for routing data among circuits coupled with the TLN 330 and external devices, such as high-capacity memory, host processors, other CGR processors, FPGA devices, and so on, that may be coupled with the interfaces.

As shown in FIG. 3 , each CGR array 310, 320 has four AGCUs (e.g., MAGCU1, AGCU12, AGCU13, and AGCU14 in CGR array 310). The AGCUs interface the TLN to the ALNs and route data from the TLN to the ALN or vice versa. Other implementations may have different numbers of AGCUs.

One of the AGCUs in each CGR array in this example is configured to be a master AGCU (MAGCU), which includes an array configuration load/unload controller for the CGR array. The MAGCU1 includes a configuration load/unload controller for CGR array 310, and MAGCU2 includes a configuration load/unload controller for CGR array 320. Some implementations may include more than one array configuration load/unload controller. In other implementations, an array configuration load/unload controller may be implemented by logic distributed among more than one AGCU. In yet other implementations, a configuration load/unload controller can be designed for loading and unloading configuration of more than one CGR array. In further implementations, more than one configuration controller can be designed for configuration of a single CGR array. Also, the configuration load/unload controller can be implemented in other portions of the system, including as a stand-alone circuit on the TLN and the ALN or ALNs.

The TLN 330 may be constructed using top-level switches (e.g., switch 311, switch 312, switch 313, switch 314, switch 315, and switch 316). If desired, the top-level switches may be coupled with at least one other top-level switch. At least some top-level switches may be connected with other circuits on the TLN, including the AGCUs, and external I/O interface 338.

Illustratively, the TLN 330 includes links (e.g., L11, L12, L21, L22) coupling the top-level switches. Data may travel in packets between the top-level switches on the links, and from the switches to the circuits on the network coupled with the switches. For example, switch 311 and switch 312 are coupled by link L11, switch 314 and switch 315 are coupled by link L12, switch 311 and switch 314 are coupled by link L13, and switch 312 and switch 313 are coupled by link L21. The links can include one or more buses and supporting control lines, including for example a chunk-wide bus (vector bus). For example, the top-level network can include data, request and response channels operable in coordination for transfer of data in any manner known in the art.

FIG. 4 illustrates an example CGR array 400, including an array of CGR units in an ALN. CGR array 400 may include several types of CGR unit 401, such as FCMUs, PMUs, PCUs, memory units, and/or compute units. For examples of the functions of these types of CGR units, see Prabhakar et al., “Plasticine: A Reconfigurable Architecture for Parallel Patterns”, ISCA 2017, Jun. 24-28, 2017, Toronto, ON, Canada.

Illustratively, each of the CGR units may include a configuration store 402 comprising a set of registers or flip-flops storing configuration data that represents the setup and/or the sequence to run a program, and that can include the number of nested loops, the limits of each loop iterator, the instructions to be executed for each stage, the source of operands, and the network parameters for the input and output interfaces. In some implementations, each CGR unit 401 comprises an FCMU. In other implementations, the array comprises both PMUs and PCUs, or memory units and compute units, arranged in a checkerboard pattern. In yet other implementations, CGR units may be arranged in different patterns.

The ALN includes switch units 403 (S), and AGCUs (each including two address generators 405 (AG) and a shared coalescing unit 404 (CU)). Switch units 403 are connected among themselves via interconnects 421 and to a CGR unit 401 with interconnects 422. Switch units 403 may be coupled with address generators 405 via interconnects 420. In some implementations, communication channels can be configured as end-to-end connections, and switch units 403 are CGR units. In other implementations, switches route data via the available links based on address information in packet headers, and communication channels establish as and when needed.

A configuration file may include configuration data representing an initial configuration, or starting state, of each of the CGR units 401 that execute a high-level program with user algorithms and functions. Program load is the process of setting up the configuration stores 402 in the CGR array 400 based on the configuration data to allow the CGR units 401 to execute the high-level program. Program load may also require loading memory units and/or PMUs.

In some implementations, a runtime processor (e.g., the portions of host processor 180 of FIG. 1 that execute runtime processes 170, which is sometimes also referred to as “runtime logic”) may perform the program load.

The ALN includes one or more kinds of physical data buses, for example a chunk-level vector bus (e.g., 512 bits of data), a word-level scalar bus (e.g., 32 bits of data), and a control bus. For instance, interconnects 421 between two switches may include a vector bus interconnect with a bus width of 512 bits, and a scalar bus interconnect with a bus width of 32 bits. A control bus can comprise a configurable interconnect that carries multiple control bits on signal routes designated by configuration bits in the CGR array's configuration file. The control bus can comprise physical lines separate from the data buses in some implementations. In other implementations, the control bus can be implemented using the same physical lines with a separate protocol or in a time-sharing procedure.

Physical data buses may differ in the granularity of data being transferred. In one implementation, a vector bus can carry a chunk that includes 16 channels of 32-bit floating-point data or 32 channels of 16-bit floating-point data (i.e., 512 bits) of data as its payload. A scalar bus can have a 32-bit payload and carry scalar operands or control information. The control bus can carry control handshakes such as tokens and other signals. The vector and scalar buses can be packet-switched, including headers that indicate a destination of each packet and other information such as sequence numbers that can be used to reassemble a file when the packets are received out of order. Each packet header can contain a destination identifier that identifies the geographical coordinates of the destination switch unit (e.g., the row and column in the array), and an interface identifier that identifies the interface on the destination switch (e.g., North, South, East, West, etc.) used to reach the destination unit.

A CGR unit 401 may have four ports (as drawn) to interface with switch units 403, or any other number of ports suitable for an ALN. Each port may be suitable for receiving and transmitting data, or a port may be suitable for only receiving or only transmitting data.

A switch unit 403, as shown in the example of FIG. 4 , may have eight interfaces. The North, South, East and West interfaces of a switch unit may be used for links between switch units 403 using interconnects 421. The Northeast, Southeast, Northwest and Southwest interfaces of a switch unit 403 may each be used to make a link with an FCMU, PCU or PMU instance using one of the interconnects 422. Two switch units 403 in each CGR array quadrant have links to an AGCU using interconnects 420. The coalescing unit 404 of the AGCU arbitrates between the address generators 405 and processes memory requests. Each of the eight interfaces of a switch unit 403 can include a vector interface, a scalar interface, and a control interface to communicate with the vector network, the scalar network, and the control network. In other implementations, a switch unit 403 may have any number of interfaces.

During execution of a graph or subgraph in a CGR array 400 after configuration, data can be sent via one or more switch units 403 and one or more interconnects 421 between the switch units to the CGR units 401 using the vector bus and vector interface(s) of the one or more switch units 403 on the ALN. A CGR array may comprise at least a part of CGR array 400, and any number of other CGR arrays coupled with CGR array 400.

A data processing operation implemented by CGR array configuration may comprise multiple graphs or subgraphs specifying data processing operations that are distributed among and executed by corresponding CGR units (e.g., FCMUs, PMUs, PCUs, AGs, and CUs).

FIG. 5 illustrates an example 500 of a PMU 510 and a PCU 520, which may be combined in an FCMU 530. PMU 510 may be directly coupled to PCU 520, or optionally via one or more switches. The FCMU 530 may include multiple ALN links, such as ALN link 423 that connects PMU 510 with PCU 520, northwest ALN link 422A and southwest ALN link 422B, which may connect to PMU 510, and southeast ALN link 422C and northeast ALN link 422D, which may connect to PCU 520.

The northwest ALN link 422A, southwest ALN link 422B, southeast ALN link 422C, and northeast ALN link 422D may connect to switches 403 as shown in FIG. 4 . Each ALN link 422A-D, 423 may include one or more scalar links, one or more vector links, and one or more control links where an individual link may be unidirectional into FCMU 530, unidirectional out of FCMU 530 or bidirectional. FCMU 530 can include FIFOs to buffer data entering and/or leaving the FCMU 530 on the links.

PMU 510 may include an address converter 514, a scratchpad memory 515, and a configuration store 518. Configuration store 518 may be loaded, for example, from a program running on host processor 180 as shown in FIG. 1 , and can configure address converter 514 to generate or convert address information for scratchpad memory 515 based on data received through one or more of the ALN links 422A-B, and/or 423. Data received through ALN links 422A-B, and/or 423 may be written into scratchpad memory 515 at addresses provided by address converter 514. Data read from scratchpad memory 515 at addresses provided by address converter 514 may be sent out on one or more of the ALN links 422A-B, and/or 423.

PCU 520 includes two or more processor stages, such as single-instruction multiple-data (SIMD) 521 through SIMD 526, and configuration store 528. The processor stages may include SIMDs, as drawn, or any other reconfigurable stages that can process data. PCU 520 may receive data through ALN links 422C-D, and/or 423, and process the data in the two or more processor stages or store the data in configuration store 528.

PCU 520 may produce data in the two or more processor stages, and transmit the produced data through one or more of the ALN links 422C-D, and/or 423. If the two or more processor stages include SIMDs, then the SIMDs may have a number of lanes of processing equal to the number of lanes of data provided by a vector interconnect of ALN links 422C-D, and/or 423.

Each stage in PCU 520 may hold one or more registers (not drawn) for short-term storage of parameters. Short-term storage, for example during one to several clock cycles or unit delays, allows for synchronization of data in a PCU pipeline.

FIG. 6 is a block diagram of a data processing system 600 including a compiler 620 that is suitable for generating a configuration file for a CGR processor having CGR units such as CGR processor 110 of FIG. 1 . As depicted, compiler 620 includes several stages to convert a high-level program with statements that define user algorithms and functions, e.g., algebraic expressions and functions, to configuration data for the CGR units. A high-level program may include source code written in programming languages like C, C++, Java, JavaScript, Python, and/or Spatial, for example. In some implementations, the high-level program may include statements that invoke various PyTorch functions.

Compiler stack 620 may take its input from application platform 610, or any other source of high-level program statements suitable for parallel processing, which provides a user interface for general users. If desired, the compiler 620 may further receive hardware description 615, for example defining the physical units in a reconfigurable data processor or CGRA processor. Application platform 610 may include libraries such as PyTorch, TensorFlow, ONNX, Caffe, and Keras to provide user-selected and configured algorithms.

Application platform 610 outputs a high-level program to compiler 620, which in turn outputs a configuration file that is executed in runtime processes 630 using reconfigurable processor 650.

Compiler 620 may include dataflow graph compiler 621, which may handle a dataflow graph, algebraic graph compiler 622, template graph compiler 623, template library 624, placer and router PNR 625, and cost estimation tool 640. In some implementations, template library 624 includes RDU abstract intermediate language (RAIL) and/or assembly language interfaces for power users.

Dataflow graph compiler 621 converts the high-level program with user algorithms and functions from application platform 610 to one or more dataflow graphs. The high-level program may be suitable for parallel processing, and therefore parts of the nodes of the dataflow graphs may be intrinsically parallel unless an edge in the graph indicates a dependency.

Dataflow graph compiler 621 may provide code optimization steps like false data dependency elimination, dead-code elimination, and constant folding. The dataflow graphs encode the data and control dependencies of the high-level program. Dataflow graph compiler 621 may support programming a reconfigurable data processor at higher or lower-level programming languages, for example from an application platform 610 to C++ and assembly language.

In some implementations, dataflow graph compiler 621 allows programmers to provide code that runs directly on the reconfigurable data processor. In other implementations, dataflow graph compiler 621 provides one or more libraries that include predefined functions like linear algebra operations, element-wise tensor operations, non-linearities, and reductions required for creating, executing, and profiling the dataflow graphs on the reconfigurable processors. Dataflow graph compiler 621 may provide an application programming interface (API) to enhance functionality available via the application platform 610.

Algebraic graph compiler 622 may include a model analyzer and compiler (MAC) level that makes high-level mapping decisions for (sub-graphs of the) dataflow graph based on hardware constraints. In some implementations, the algebraic graph compiler 622 may support various application frontends such as Samba, JAX, and TensorFlow/HLO. If desired, the algebraic graph compiler 622 may transform the graphs via autodiff and GradNorm, perform stitching between sub-graphs, interface with template generators for performance and latency estimation, convert dataflow graph operations to arithmetic or algebraic intermediate representation (AIR) operations, perform tiling, sharding (database partitioning) and other operations, and model or estimate the parallelism that can be achieved on the dataflow graph.

Algebraic graph compiler 622 may further include an arithmetic or algebraic intermediate representation (AIR) level that translates high-level graph and mapping decisions provided by the MAC level into explicit AIR/Tensor statements and one or more corresponding algebraic graphs. Key responsibilities of the AIR level include legalizing the graph and mapping decisions of the MAC, expanding data parallel, tiling, metapipe, region instructions provided by the MAC, inserting stage buffers and skip buffers, eliminating redundant operations, buffers and sections, and optimizing for resource use, latency, and throughput.

Thus, algebraic graph compiler 622 replaces the user program statements of a dataflow graph by AIR/Tensor statements of an AIR/Tensor computation graph (AIR graph).

Template graph compiler 623 may translate AIR/Tensor statements of an AIR graph into template library intermediate representation (TLIR) statements of a TLIR graph, optimizing for the target hardware architecture into unplaced variable-sized units (referred to as logical CGR units or just logical units) suitable for PNR 625. Such a TLIR graph is sometimes also referred to as an “operation unit graph” and the unplaced-variable-sized units as “logical units”. The logical units may include ports, and logical edges in the operation unit graph may couple the logical units at the ports.

Template graph compiler 623 may allocate metapipelines for sections of the template dataflow statements and corresponding sections of unstitched template computation graph. Template graph compiler 623 may add further information (name, inputs, input names and dataflow description) for PNR 625 and make the graph physically realizable through each performed step. For example, template graph compiler 623 may provide translation of AIR graphs to specific model operation templates such as for general matrix multiplication (GeMM). An implementation may convert part or all intermediate representation operations to templates, stitch templates into the dataflow and control flow, insert necessary buffers and layout transforms, generate test data and optimize for hardware use, latency, and throughput.

Implementations may use templates for common operations. Templates may be implemented using assembly language, RAIL, or similar. RAIL is comparable to assembly language in that memory units and compute units are separately programmed, but it can provide a higher level of abstraction and compiler intelligence via a concise performance-oriented domain-specific language for CGR array templates. RAIL enables template writers and external power users to control interactions between logical compute units and memory units, which are commonly referred to as logical units, with high-level expressions without the need to manually program capacity splitting, register allocation, etc. The logical compute units and memory units also enable stage/register allocation, context splitting, transpose slotting, resource virtualization and mapping to multiple physical compute units and memory units (e.g., PCUs and PMUs).

Template library 624 may include an assembler that provides an architecture-independent low-level programming interface as well as optimization and code generation for the target hardware. Responsibilities of the assembler may include address expression compilation, intra-unit resource allocation and management, making a template graph physically realizable with target-specific rules, low-level architecture-specific transformations and optimizations, and architecture-specific code generation. In some implementations, the assembler may generate assembler code for a logical unit, whereby the assembler code is associated with a data operation that is to be executed by the logical unit. The logical units of an operation unit graph may include (e.g., store) the assembler code that is associated with the respective data operations of the respective logical units, if desired.

The template graph compiler 623 may also determine control signals, as well as control gates that are required to enable the CGR units (whether logical or physical) to coordinate dataflow between the CGR units in the CGR array of a CGR processor.

As shown in FIG. 6 , compiler 620 may include a cost estimation tool 640. The cost estimation tool 640 may estimate a cost of implementing an operation unit graph on reconfigurable processor 650.

Illustratively, cost estimation tool 640 may receive the operation unit graph from the template graph compiler 623 directly and/or through the template library 624. The operation unit graph may include logical units that perform data operations and have ports that are coupled by logical edges. For example, the operation unit graph may include a first logical unit that performs a first data operation and has a first port, a second logical unit that performs a second data operation and has a second port, and a logical edge that connects the first port with the second port. The cost estimation tool 640 may provide the cost estimation for implementing the operation unit graph on reconfigurable processor 650 to PNR 625.

PNR 625 translates and maps logical (i.e., unplaced physically realizable) units (e.g., the nodes of the operation unit graph) and logical edges (e.g., the edges of the operation unit graph) to a physical layout of reconfigurable processor 650, e.g., a physical array of CGR units in a semiconductor chip. PNR 625 also determines physical data channels to enable communication among the CGR units and between the CGR units and circuits coupled via the TLN; allocates ports on the CGR units and switches; provides configuration data and initialization data for the target hardware; and produces configuration files, e.g., processor-executable format (PEF) files.

If desired, PNR 625 may provide bandwidth calculations, allocate network interfaces such as AGCUs and virtual address generators (VAGs), provide configuration data that allows AGCUs and/or VAGs to perform address translation, and control ALN switches and data routing. PNR 625 may provide its functionality in multiple steps and may include multiple modules (not shown in FIG. 6 ) to provide the multiple steps, e.g., a placer, a router, a port allocator, and a PEF file generator.

Illustratively, PNR 625 may receive its input data in various ways. For example, it may receive parts of its input data from any of the earlier modules (dataflow graph compiler 621, algebraic graph compiler 622, template graph compiler 623, and/or template library 624). In some implementations, an earlier module, such as template graph compiler 623, may have the task of preparing all information for PNR 625 and no other units provide PNR input data directly. As shown in FIG. 6 , PNR 625 may receive a cost estimation for implementing the operation unit graph on reconfigurable processor 650 from cost estimation tool 640.

Further implementations of compiler 620 provide for an iterative process, for example by feeding information from PNR 625 back to an earlier module (e.g., to cost estimation tool 640 or to algebraic graph compiler 622). For example, in some implementations, the earlier module may execute a new compilation step in which it uses physically realized results rather than estimates of cost estimation tool 640 or placeholders for physically realizable circuits. As shown in FIG. 6 , PNR 625 may feed information regarding the physically realized circuits back to algebraic graph compiler 622.

Memory allocations represent the creation of logical memory spaces in on-chip and/or off-chip memories for data required to implement the dataflow graph, and these memory allocations are specified in the configuration file. Memory allocations define the type and the number of hardware circuits (functional units, storage, or connectivity components). Main memory (e.g., DRAM) may be off-chip memory, and scratchpad memory (e.g., SRAM) is on-chip memory inside a CGR array. Other memory types for which the memory allocations can be made for various access patterns and layouts include cache, read-only look-up tables (LUTs), serial memories (e.g., FIFOs), and register files.

Compiler 620 binds memory allocations to unplaced memory units and binds operations specified by operation nodes in the dataflow graph to unplaced compute units, and these bindings may be specified in the configuration data. In some implementations, compiler 620 partitions parts of a dataflow graph into memory subgraphs and compute subgraphs, and specifies these subgraphs in the PEF file. A memory subgraph may comprise address calculations leading up to a memory access. A compute subgraph may comprise all other operations in the parent graph. In one implementation, a parent graph is broken up into multiple memory subgraphs and exactly one compute subgraph. A single parent graph can produce one or more memory subgraphs, depending on how many memory accesses exist in the original loop body. In cases where the same memory addressing logic is shared across multiple memory accesses, address calculation may be duplicated to create multiple memory subgraphs from the same parent graph.

Compiler 620 generates the configuration files with configuration data (e.g., a bit stream) for the placed positions and the routed data and control networks. In one implementation, this includes assigning coordinates and communication resources of the physical CGR units by placing and routing unplaced units onto the array of CGR units while maximizing bandwidth and minimizing latency.

As mentioned above, the cost estimation tool 640 may estimate a cost of implementing an operation unit graph on reconfigurable processor 650. FIG. 7 is a diagram of an illustrative operation unit graph 700. The operation unit graph 700 may include logical units 710 to 714, 720 to 729, and 730 to 732.

The logical units may perform data operations. The data operations may include configuration load, configuration unload, arithmetic operations, storage operations, just to name a few. If desired, each logical unit may include assembler code that is associated with the data operation.

Illustratively, the operation unit graph 700 may include different types of logical units. For example, the logical units may include a compute unit or a memory unit. As shown in FIG. 7 , the operation unit graph 700 may include AGCUs 710 to 714, PMUs 720 to 729, and PCUs 730 to 732.

The logical units may have ports. Illustratively, the logical units may have one or more input ports and/or one or more output ports. As an example, logical units 710, 712, 713 may have one or more output ports. As another example, logical units 711, 714 may have one or more input ports. As yet another example, logical units 720 to 732 may have one or more input ports and one or more output ports.

Note that logical units 710, 712, 713 are shown without input ports and logical units 711, 714 are shown without output ports. However, logical units 710, 712, 713 have input ports and logical units 711, 714 have output ports. The input ports of logical unit 710, 712, 713 and the output ports of logical units 711, 714 may be coupled outside of the operation unit graph 700 (e.g., via a network) and are omitted hereinafter for simplicity.

As shown in FIG. 7 , the operation unit graph 700 may include logical edges 750, 751, 752. The logical edges may connect the logical units at the ports. As an example, logical edges 750 may connect an output port of a logical unit (e.g., logical unit 710, 712, 713) having one or more output ports with an input port of another logical unit (e.g., logical unit 720, 721, 726, 727). As another example, logical edges 751 may connect an output port of a logical unit (e.g., logical unit 722, 723, etc.) having one or more input ports and one or more output ports with an input port of another logical unit (e.g., logical unit 730, 725, etc.) having one or more input ports and one or more output ports. As yet another example, logical edges 752 may connect an output port of a logical unit (e.g., logical unit 725, 729) having one or more input ports and one or more output ports with an input port of another logical unit (e.g., logical unit 711, 714, etc.) having one or more input ports.

In some implementations, the operation unit graph may include logical edges that represent nets. These nets may have a fanout greater than one. For example, the logical edge that connects to the output port of logical unit 730 is shown as a net of fanout two that feeds into logical units 723 and 724. In other implementations logical edges are shown as connections having exactly one fan-in and one fanout. For example, the connection from the output port of logical unit 730 may be shown as two logical edges, a first logical edge from logical unit 730 to logical unit 723 and a second logical edge from logical unit 730 to logical unit 724.

FIG. 8 is a diagram of an illustrative cost estimation tool 810 that receives an operation unit graph 805 (e.g., operation unit graph 700 of FIG. 7 ) and architectural specifications 860 and provides logical edge bandwidths and timing groups of logical edges as a cost estimation (e.g., in form of bandwidth model 850) of implementing the operation unit graph on a reconfigurable processor (e.g., CGR processor 110 having arrays of CGR units 120 of FIG. 1 or reconfigurable processor 650 of FIG. 6 ) to placer and router 870. As shown in FIG. 8 , the illustrative cost estimation tool 810 may include a port bandwidth determination unit 820, a logical edge bandwidth determination unit 830, and a timing group determination unit 840.

For example, consider the scenario in which the cost estimation tool 810 is configured to receive an operation unit graph 805 having a first logical unit that performs a first data operation and has a first port, a second logical unit that performs a second data operation and has a second port, and a logical edge that connects the first port with the second port. Consider further that the first logical unit comprises first assembler code that is associated with the first data operation, and that the second logical unit comprises second assembler code that is associated with the second data operation.

In this scenario, the port bandwidth determination unit 820 may be configured to determine a first upper bandwidth limit of the first port based on the first data operation and a second upper bandwidth limit of the second port based on the second data operation. For example, the port bandwidth determination unit 820 may be configured to determine a pattern in the first assembler code and determine the first upper bandwidth limit of the first port based on the pattern in the first assembler code. Similarly, the port bandwidth determination unit 820 may be configured to determine a pattern in the second assembler code and determine the second upper bandwidth limit of the second port based on the pattern in the second assembler code.

As an example, in response to determining that the pattern in the assembler code comprises a sequence-id based address calculation, the port bandwidth determination unit 820 may determine the first upper bandwidth limit of the first port based on a length of an input first-in first-out (FIFO) buffer of the first port divided by a number of arithmetic logic unit (ALU) stages used for address calculation. For example, the first upper bandwidth limit (BW) may be determined as

${BW} = \frac{D}{C_{0} + {C_{1} \times S}}$

where D is the input FIFO depth of the first port, C₀ and C₁ are architecture specific constants that account for internal latencies, and S is the number of ALU stages being used for address calculation based on the sequence ID.

As another example, in response to determining that the pattern in the assembler code comprises bubbles in a pipeline of a memory unit, the port bandwidth determination unit 820 may determine the first upper bandwidth limit of the first port based on a number of vectors processed by the memory unit to trigger a token generation divided by a sum of a constant that is based on the bubbles being inserted into the pipeline and the number of vectors processed by the memory unit to trigger the token generation. For example, the first upper bandwidth limit (BW) may be determined as

${BW} = \frac{V}{V + C_{2}}$

where V is the number of vectors being processed in the logical unit to trigger an internal token being generated in the logical unit. C₂ is an architectural specific constant to account for the bubbles being inserted in the logical unit pipeline when a logical unit internal token is being generated. V is derived from the assembler codes that describe token generation.

As yet another example, in response to determining that the pattern in the assembler code comprises a dequeue operation of a memory unit, the port bandwidth determination unit 820 may determine the first upper bandwidth limit of the first port based on one divided by a number of memory access operations that occur before the memory unit consumes one entry from an input FIFO buffer of the first port. For example, the first upper bandwidth limit (BW) may be determined as

${BW} = \frac{1}{SA}$

where SA is a number of SRAM memory access operations that occur before the memory unit consumes one entry from the input FIFO.

As yet another example, in response to determining that the pattern in the assembler code comprises a dequeue operation of a compute unit, the port bandwidth determination unit 820 may determine the first upper bandwidth limit of the first port based on one divided by a number of enable signals that flow through a number of arithmetic logic unit (ALU) stages. For example, the first upper bandwidth limit (BW) may be determined as

${BW} = \frac{1}{OP}$

where OP is a number of enables that flows through the ALU stages of the logical unit.

As yet another example, in response to determining that the pattern in the assembler code comprises a tail function of a compute unit or a systolic operation of a compute unit, the port bandwidth determination unit 820 may determine the first upper bandwidth limit of the first port based on a number of vectors being processed by the compute unit divided by a sum of a constant and a latency of the compute unit. For example, the first upper bandwidth limit (BW) may be determined as

${BW} = \frac{V}{C + L}$

where V is a number of vectors flowing into the logical unit, C is a duration for consuming the vectors, and L is a constant representing an internal delay of the logical unit.

In the scenario described above, the logical edge bandwidth determination unit 830 may be configured to determine a logical edge bandwidth of the logical edge based on the first and second upper bandwidth limits. The logical edge bandwidth is indicative of the static bandwidth that a logical edge requires for the template that includes the first and second logical units to run at full throughput, assuming that the logical edge receives inputs from the first logical unit at the maximum bandwidth that the second logical unit is capable of sinking. The logical edge bandwidth is placement agnostic and assumes that inputs from the first port are always available and outputs to the second port are never back-pressured due to ALN network congestion.

As an example, the logical edge bandwidth determination unit 830 may be configured to determine the logical edge bandwidth of the logical edge as the minimum of the upper bandwidth limit of the first port and the upper bandwidth limit of the second port. For example, the logical bandwidth limit of the logical edge may be 1.0 if the first logical unit can produce an output vector every cycle and the second logical unit can consume an input vector every cycle. In the operation unit graph 700 of FIG. 7 , the logical edge bandwidth determination unit 830 may be configured to determine that the logical edge between logical unit 710 and logical unit 720, the logical edge between logical units 710 and 721, the logical edge between logical units 720 and 722, and the logical edge between logical units 721 have an upper bandwidth limit of 0.5 and 722, and that the logical edge between logical units 725 and 711 has an upper bandwidth limit of 1.0.

In the scenario described above, the timing group determination unit 840 may be configured to determine a timing group from a predetermined number of timing groups for the logical edge. For example, the operation unit graph 805 may include logical edges that are active during different execution phases of the operation unit graph 805 such that any two logical edges that are in different timing groups are substantially active non-concurrently. In other words, the time when two logical edges that are in different timing groups are active concurrently is negligible, whereas any two logical edges in the same timing groups have a very high chance of being active at the same time.

For example, the logical edges 750 of operation unit graph 700 of FIG. 7 may be active during an initialization phase (INIT), the logical edges 751 during an execution phase (EXEC), and the logical edges 752 during a final phase (FINAL) of the execution of the operation unit graph 700. Any two logical edges in the initialization phase or any two logical edges in the execution phase or any two edges in the final phase have a high chance of being active at the same time. However, a first logical edge in the initialization phase has a very low chance of being active at the same time as a second logical edge in the execution phase or as a third logical edge in the final phase, the second logical edge in the execution phase has a very low chance of being active at the same time as the first logical edge in the initialization phase or as the third logical edge in the final phase, and the third logical edge in the final phase has a very low chance of being active at the same time as the first logical edge in the initialization phase or as the second logical edge in the execution phase.

For determining the timing group from the predetermined number of timing groups for the logical edge, the timing group determination unit 840 may be configured to determine whether the logical edge is active during a first execution phase of the operation unit graph 805 or during a second execution phase of the operation unit graph 805, whereby the first and second execution phases are essentially non-overlapping. Thus, in response to determining that the logical edge is active during the first execution phase, the timing group determination unit 840 may assign a first timing group of the predetermined number of timing groups to the logical edge, and in response to determining that the logical edge is active during the second execution phase, the timing group determination unit 840 may assign a second timing group of the predetermined number of timing groups to the logical edge.

For example, the timing group determination unit 840 may be configured to determine that the logical edge between logical unit 710 and logical unit 720 of FIG. 7 and the logical edge between logical unit 710 and logical unit 721 are in timing group INIT, that the logical edge between logical units 720 and 722 and the logical edge between logical units 721 and 722 are in timing group EXEC, and that the logical edge between logical units 725 and 711 is in timing group FINAL.

Illustratively, the cost estimation tool 810 may provide the logical edge bandwidth and the timing group in a bandwidth model 850 as a cost estimation of implementing the operation unit graph 805 on the reconfigurable processor to placer and router 870.

FIG. 9 is a flowchart showing illustrative operations that a cost estimation tool (e.g., cost estimation 810 of FIG. 8 ) performs for estimating a cost of implementing an operation unit graph (e.g., operation unit graph 805 of FIG. 8 ) on a reconfigurable processor (e.g., reconfigurable processor 650 of FIG. 6 or CGR processor 110 of FIG. 1 ).

During operation 910, the cost estimation tool may receive the operation unit graph comprising a first logical unit that performs a first data operation and has a first port, a second logical unit that performs a second data operation and has a second port, and a logical edge that connects the first port with the second port.

For example, the cost estimation tool 810 of FIG. 8 may receive operation unit graph 805 or operation unit graph 700 of FIG. 7 . The operation unit graph 700 of FIG. 7 includes logical unit 722 that may perform a memory read operation of data and provide the data via logical edge 751 to logical unit 730 that may perform a compute operation on the data.

During operation 920, the cost estimation tool may determine a timing group from a predetermined number of timing groups for the logical edge. For example, the timing group determination unit 840 of cost estimation tool 810 of FIG. 8 may determine the timing group of each logical edge of operation unit graph 805 or of operation unit graph 700 of FIG. 7 based on whether the logical edge is active during an initialization phase (INIT), during a final phase (FINAL), or during an execution phase (EXEC). Illustratively, the timing group determination unit 840 may determine that logical edges 750 of operation unit graph 700 of FIG. 7 are in timing group INIT, that logical edges 751 are in timing group EXEC, and that logical edges 752 are in timing group FINAL.

During operation 930, the cost estimation tool may determine a first upper bandwidth limit of the first port based on the first data operation. For example, the port bandwidth determination unit 820 of cost estimation tool 810 of FIG. 8 may determine an upper bandwidth limit of the output port of logical unit 722 of FIG. 7 based on the data operation of logical unit 722. Illustratively, the port bandwidth determination unit 820 of FIG. 8 may determine the upper bandwidth of the output port of logical unit 722 to be 1.0.

During operation 940, the cost estimation tool may determine a second upper bandwidth limit of the second port based on the second data operation. For example, the port bandwidth determination unit 820 of cost estimation tool 810 of FIG. 8 may determine an upper bandwidth limit of the input port of logical unit 730 of FIG. 7 based on the data operation of logical unit 730. Illustratively, the port bandwidth determination unit 820 of FIG. 8 may determine the upper bandwidth of the input port of logical unit 730 to be 1.0.

During operation 950, the cost estimation tool may determine a logical edge bandwidth of the logical edge based on the first and second upper bandwidth limits. For example, the logical edge bandwidth determination unit 830 of cost estimation tool 810 of FIG. 8 may determine an upper bandwidth limit of the logical edge 751 between logical units 722 and 730 of FIG. 7 based on the upper bandwidth of the output port of logical unit 722 and the upper bandwidth limit of the input port of logical unit 730. Illustratively, the logical edge bandwidth determination unit 830 of FIG. 8 may determine the upper bandwidth of the logical edge as the minimum of the upper bandwidth of the input port of logical unit 730 and the upper bandwidth of the output port of logical unit 722. In the event in which the upper bandwidth limit of the input port of logical unit 730 and the upper bandwidth limit of the output port of logical unit 722 are both 1.0, the upper bandwidth of the logical edge between logical units 722 and 730 may be determined to be 1.0.

During operation 960, the cost estimation tool may provide the logical edge bandwidth and the timing group as a cost estimation of implementing the operation unit graph on the reconfigurable processor. For example, the cost estimation tool 810 of FIG. 8 may provide the logical edge bandwidth and the timing group of each edge as bandwidth model 850 to placer and router 870.

Illustratively, for determining the timing group from the predetermined number of timing groups for the logical edge, the cost estimation tool may determine whether the logical edge is active during a first execution phase of the operation unit graph or during a second execution phase of the operation unit graph, wherein the first and second execution phases are non-overlapping.

By way of example, the cost estimation tool may, in response to determining that the logical edge is active during the first execution phase, assign a first timing group of the predetermined number of timing groups to the logical edge, and in response to determining that the logical edge is active during the second execution phase, assigning a second timing group of the predetermined number of timing groups to the logical edge.

In some implementations, the first logical unit comprises assembler code that is associated with the first data operation. In these implementations, the cost estimation tool may determine a pattern in the assembler code for determining the first upper bandwidth limit of the first port based on the first data operation.

If desired, a non-transitory computer-readable storage medium includes instructions that, when executed by a processing unit (e.g., host processor 180 of FIG. 1 ), cause the processing unit to operate a cost estimation tool (e.g., the cost estimation tool 640 of FIG. 6 or the cost estimation tool 810 of FIG. 8 ) for estimating a cost of implementing an operation unit graph on a reconfigurable processor by performing operation 910 to 960 of FIG. 9 .

The instructions may include receiving the operation unit graph having logical edges, logical units, and ports at associated logical units, wherein the logical edges connect with the logical units at the ports, and wherein the logical units perform data operations, determining upper bandwidth limits of the ports based on the data operations of the associated logical units, determining logical edge bandwidths of the logical edges based on the upper bandwidth limits of the ports at which the logical edges connect with the logical units, determining timing groups from a predetermined number of timing groups for the logical edges, and providing the logical edge bandwidths and the timing groups of the logical edges as a cost estimation of implementing the operation unit graph on the reconfigurable processor.

While the present technology is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims.

As will be appreciated by those of ordinary skill in the art, aspects of the presented technology may be embodied as a system, device, method, or computer program product apparatus. Accordingly, elements of the present disclosure may be implemented entirely in hardware, entirely in software (including firmware, resident software, micro-code, or the like) or in software and hardware that may all generally be referred to herein as a “apparatus,” “circuit,” “circuitry,” “module,” “computer,” “logic,” “FPGA,” “unit,” “system,” or other terms.

Furthermore, aspects of the presented technology may take the form of a computer program product embodied in one or more computer-readable medium(s) having computer program code stored thereon. The phrases “computer program code” and “instructions” both explicitly include configuration information for a CGRA, an FPGA, or other programmable logic as well as traditional binary computer instructions, and the term “processor” explicitly includes logic in a CGRA, an FPGA, or other programmable logic configured by the configuration information in addition to a traditional processing core. Furthermore, “executed” instructions explicitly includes electronic circuitry of a CGRA, an FPGA, or other programmable logic performing the functions for which they are configured by configuration information loaded from a storage medium as well as serial or parallel execution of instructions by a traditional processing core.

Any combination of one or more computer-readable storage medium(s) may be utilized. A computer-readable storage medium may be embodied as, for example, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or other like storage devices known to those of ordinary skill in the art, or any suitable combination of computer-readable storage mediums described herein. In the context of this document, a computer-readable storage medium may be any tangible medium that can contain, or store, a program and/or data for use by or in connection with an instruction execution system, apparatus, or device. Even if the data in the computer-readable storage medium requires action to maintain the storage of data, such as in a traditional semiconductor-based dynamic random-access memory, the data storage in a computer-readable storage medium can be considered to be non-transitory.

A computer data transmission medium, such as a transmission line, a coaxial cable, a radio-frequency carrier, and the like, may also be able to store data, although any data storage in a data transmission medium can be said to be transitory storage. Nonetheless, a computer-readable storage medium, as the term is used herein, does not include a computer data transmission medium.

Computer program code for carrying out operations for aspects of the present technology may be written in any combination of one or more programming languages, including object-oriented programming languages such as Java, Python, C++, or the like, conventional procedural programming languages, such as the “C” programming language or similar programming languages, or low-level computer languages, such as assembly language or microcode. In addition, the computer program code may be written in VHDL, Verilog, or another hardware description language to generate configuration instructions for an FPGA, CGRA IC, or other programmable logic.

The computer program code if converted into an executable form and loaded onto a computer, FPGA, CGRA IC, or other programmable apparatus, produces a computer implemented method. The instructions which execute on the computer, FPGA, CGRA IC, or other programmable apparatus may provide the mechanism for implementing some or all of the functions/acts specified in the flowchart and/or block diagram block or blocks. In accordance with various implementations, the computer program code may execute entirely on the user's device, partly on the user's device and partly on a remote device, or entirely on the remote device, such as a cloud-based server. In the latter scenario, the remote device may be connected to the user's device through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). The computer program code stored in/on (i.e. embodied therewith) the non-transitory computer-readable medium produces an article of manufacture.

The computer program code, if executed by a processor, causes physical changes in the electronic devices of the processor which change the physical flow of electrons through the devices. This alters the connections between devices which changes the functionality of the circuit. For example, if two transistors in a processor are wired to perform a multiplexing operation under control of the computer program code, if a first computer instruction is executed, electrons from a first source flow through the first transistor to a destination, but if a different computer instruction is executed, electrons from the first source are blocked from reaching the destination, but electrons from a second source are allowed to flow through the second transistor to the destination. So, a processor programmed to perform a task is transformed from what the processor was before being programmed to perform that task, much like a physical plumbing system with different valves can be controlled to change the physical flow of a fluid.

Example 1 is a method of operating a cost estimation tool for estimating a cost of implementing an operation unit graph on a reconfigurable processor, comprising: receiving the operation unit graph comprising a first logical unit that performs a first data operation and has a first port, a second logical unit that performs a second data operation and has a second port, and a logical edge that connects the first port with the second port; determining a timing group from a predetermined number of timing groups for the logical edge; determining a first upper bandwidth limit of the first port based on the first data operation; determining a second upper bandwidth limit of the second port based on the second data operation; determining a logical edge bandwidth of the logical edge based on the first and second upper bandwidth limits; and providing the logical edge bandwidth and the timing group as a cost estimation of implementing the operation unit graph on the reconfigurable processor.

In Example 2, the reconfigurable processor of Example 1 comprises arrays of coarse-grained reconfigurable (CGR) units.

In Example 3, one of the first and second logical units of Example 1 comprises a compute unit or a memory unit.

In Example 4, determining the timing group from the predetermined number of timing groups for the logical edge of Example 1 further comprises determining whether the logical edge is active during a first execution phase of the operation unit graph or during a second execution phase of the operation unit graph, wherein the first and second execution phases are non-overlapping.

In Example 5, the method of Example 4 further comprises: in response to determining that the logical edge is active during the first execution phase, assigning a first timing group of the predetermined number of timing groups to the logical edge; and in response to determining that the logical edge is active during the second execution phase, assigning a second timing group of the predetermined number of timing groups to the logical edge.

In Example 6, the first logical unit of Example 1 comprises assembler code that is associated with the first data operation.

In Example 7, determining the first upper bandwidth limit of the first port based on the first data operation of Example 6 further comprises determining a pattern in the assembler code.

In Example 8, the method of Example 7 further comprises in response to determining that the pattern in the assembler code comprises a sequence-id based address calculation, determining the first upper bandwidth limit of the first port based on a length of an input first-in first-out (FIFO) buffer of the first port divided by a number of arithmetic logic unit (ALU) stages used for address calculation.

In Example 9, the method of Example 7 further comprises in response to determining that the pattern in the assembler code comprises bubbles in a pipeline of a memory unit, determining the first upper bandwidth limit of the first port based on a number of vectors processed by the memory unit to trigger a token generation divided by a sum of a constant that is based on the bubbles being inserted into the pipeline and the number of vectors processed by the memory unit to trigger the token generation.

In Example 10, the method of Example 7 further comprises in response to determining that the pattern in the assembler code comprises a dequeue operation of a memory unit, determining the first upper bandwidth limit of the first port based on one divided by a number of memory access operations that occur before the memory unit consumes one entry from an input FIFO buffer of the first port.

In Example 11, the method of Example 7 further comprises in response to determining that the pattern in the assembler code comprises a dequeue operation of a compute unit, determining the first upper bandwidth limit of the first port based on one divided by a number of enable signals that flow through a number of arithmetic logic unit (ALU) stages.

In Example 12, the method of Example 7 further comprises in response to determining that the pattern in the assembler code comprises a tail function of a compute unit or a systolic operation of a compute unit, determining the first upper bandwidth limit of the first port based on a number of vectors being processed by the compute unit divided by a sum of a constant and a latency of the compute unit.

Example 13 is a system for implementing an operation unit graph on a reconfigurable processor, comprising a cost estimation tool for estimating a cost of implementing the operation unit graph on the reconfigurable processor, wherein the cost estimation tool is configured to: receive the operation unit graph that comprises a first logical unit that performs a first data operation and has a first port, a second logical unit that performs a second data operation and has a second port, and a logical edge that connects the first port with the second port; determine a timing group from a predetermined number of timing groups for the logical edge; determine a first upper bandwidth limit of the first port based on the first data operation; determine a second upper bandwidth limit of the second port based on the second data operation; determine a logical edge bandwidth of the logical edge based on the first and second upper bandwidth limits; and provide the logical edge bandwidth and the timing group as a cost estimation of implementing the operation unit graph on the reconfigurable processor.

In Example 14, the reconfigurable processor of Example 13 comprises arrays of coarse-grained reconfigurable (CGR) units.

In Example 15, one of the first and second logical units of Example 13 comprises a compute unit or a memory unit.

In Example 16, the cost estimation tool of Example 13, for determining the timing group from the predetermined number of timing groups for the logical edge, is further configured to determine whether the logical edge is active during a first execution phase of the operation unit graph or during a second execution phase of the operation unit graph, wherein the first and second execution phases are non-overlapping.

In Example 17, the cost estimation tool of Example 16 is further configured to: in response to determining that the logical edge is active during the first execution phase, assign a first timing group of the predetermined number of timing groups to the logical edge; and in response to determining that the logical edge is active during the second execution phase, assign a second timing group of the predetermined number of timing groups to the logical edge.

In Example 18, the first logical unit of Example 13 comprises assembler code that is associated with the first data operation.

In Example 19, the cost estimation tool of Example 18, for determining the first upper bandwidth limit of the first port based on the first data operation, is further configured to: determine a pattern in the assembler code; and determine the first upper bandwidth limit of the first port based on the pattern in the assembler code.

Example 20 is a non-transitory computer-readable storage medium including instructions that, when executed by a processing unit, cause the processing unit to operate a cost estimation tool for estimating a cost of implementing an operation unit graph on a reconfigurable processor, the instructions comprising: receiving the operation unit graph having logical edges, logical units, and ports at associated logical units, wherein the logical edges connect with the logical units at the ports, and wherein the logical units perform data operations; determining timing groups from a predetermined number of timing groups for the logical edges; determining upper bandwidth limits of the ports based on the data operations of the associated logical units; determining logical edge bandwidths of the logical edges based on the upper bandwidth limits of the ports at which the logical edges connect with the logical units; and providing the logical edge bandwidths and the timing groups of the logical edges as a cost estimation of implementing the operation unit graph on the reconfigurable processor. 

What is claimed is:
 1. A method of operating a cost estimation tool for estimating a cost of implementing an operation unit graph on a reconfigurable processor, comprising: receiving the operation unit graph comprising a first logical unit that performs a first data operation and has a first port, a second logical unit that performs a second data operation and has a second port, and a logical edge that connects the first port with the second port; determining a timing group from a predetermined number of timing groups for the logical edge; determining a first upper bandwidth limit of the first port based on the first data operation; determining a second upper bandwidth limit of the second port based on the second data operation; determining a logical edge bandwidth of the logical edge based on the first and second upper bandwidth limits; and providing the logical edge bandwidth and the timing group as a cost estimation of implementing the operation unit graph on the reconfigurable processor.
 2. The method of claim 1, wherein the reconfigurable processor comprises arrays of coarse-grained reconfigurable (CGR) units.
 3. The method of claim 1, wherein one of the first and second logical units comprises a compute unit or a memory unit.
 4. The method of claim 1, wherein determining the timing group from the predetermined number of timing groups for the logical edge further comprises: determining whether the logical edge is active during a first execution phase of the operation unit graph or during a second execution phase of the operation unit graph, wherein the first and second execution phases are non-overlapping.
 5. The method of claim 4, further comprising: in response to determining that the logical edge is active during the first execution phase, assigning a first timing group of the predetermined number of timing groups to the logical edge; and in response to determining that the logical edge is active during the second execution phase, assigning a second timing group of the predetermined number of timing groups to the logical edge.
 6. The method of claim 1, wherein the first logical unit comprises assembler code that is associated with the first data operation.
 7. The method of claim 6, wherein determining the first upper bandwidth limit of the first port based on the first data operation further comprises: determining a pattern in the assembler code.
 8. The method of claim 7, further comprising: in response to determining that the pattern in the assembler code comprises a sequence-id based address calculation, determining the first upper bandwidth limit of the first port based on a length of an input first-in first-out (FIFO) buffer of the first port divided by a number of arithmetic logic unit (ALU) stages used for address calculation.
 9. The method of claim 7, further comprising: in response to determining that the pattern in the assembler code comprises bubbles in a pipeline of a memory unit, determining the first upper bandwidth limit of the first port based on a number of vectors processed by the memory unit to trigger a token generation divided by a sum of a constant that is based on the bubbles being inserted into the pipeline and the number of vectors processed by the memory unit to trigger the token generation.
 10. The method of claim 7, further comprising: in response to determining that the pattern in the assembler code comprises a dequeue operation of a memory unit, determining the first upper bandwidth limit of the first port based on one divided by a number of memory access operations that occur before the memory unit consumes one entry from an input FIFO buffer of the first port.
 11. The method of claim 7, further comprising: in response to determining that the pattern in the assembler code comprises a dequeue operation of a compute unit, determining the first upper bandwidth limit of the first port based on one divided by a number of enable signals that flow through a number of arithmetic logic unit (ALU) stages.
 12. The method of claim 7, further comprising: in response to determining that the pattern in the assembler code comprises a tail function of a compute unit or a systolic operation of a compute unit, determining the first upper bandwidth limit of the first port based on a number of vectors being processed by the compute unit divided by a sum of a constant and a latency of the compute unit.
 13. A system for implementing an operation unit graph on a reconfigurable processor, comprising: a cost estimation tool for estimating a cost of implementing the operation unit graph on the reconfigurable processor, wherein the cost estimation tool is configured to: receive the operation unit graph that comprises a first logical unit that performs a first data operation and has a first port, a second logical unit that performs a second data operation and has a second port, and a logical edge that connects the first port with the second port; determine a timing group from a predetermined number of timing groups for the logical edge; determine a first upper bandwidth limit of the first port based on the first data operation; determine a second upper bandwidth limit of the second port based on the second data operation; determine a logical edge bandwidth of the logical edge based on the first and second upper bandwidth limits; and provide the logical edge bandwidth and the timing group as a cost estimation of implementing the operation unit graph on the reconfigurable processor.
 14. The system of claim 13, wherein the reconfigurable processor comprises arrays of coarse-grained reconfigurable (CGR) units.
 15. The system of claim 13, wherein one of the first and second logical units comprises a compute unit or a memory unit.
 16. The system of claim 13, wherein the cost estimation tool, for determining the timing group from the predetermined number of timing groups for the logical edge, is further configured to: determine whether the logical edge is active during a first execution phase of the operation unit graph or during a second execution phase of the operation unit graph, wherein the first and second execution phases are non-overlapping.
 17. The system of claim 16, wherein the cost estimation tool is further configured to: in response to determining that the logical edge is active during the first execution phase, assign a first timing group of the predetermined number of timing groups to the logical edge; and in response to determining that the logical edge is active during the second execution phase, assign a second timing group of the predetermined number of timing groups to the logical edge.
 18. The system of claim 13, wherein the first logical unit comprises assembler code that is associated with the first data operation.
 19. The system of claim 18, wherein the cost estimation tool, for determining the first upper bandwidth limit of the first port based on the first data operation, is further configured to: determine a pattern in the assembler code; and determine the first upper bandwidth limit of the first port based on the pattern in the assembler code.
 20. A non-transitory computer-readable storage medium including instructions that, when executed by a processing unit, cause the processing unit to operate a cost estimation tool for estimating a cost of implementing an operation unit graph on a reconfigurable processor, the instructions comprising: receiving the operation unit graph having logical edges, logical units, and ports at associated logical units, wherein the logical edges connect with the logical units at the ports, and wherein the logical units perform data operations; determining timing groups from a predetermined number of timing groups for the logical edges; determining upper bandwidth limits of the ports based on the data operations of the associated logical units; determining logical edge bandwidths of the logical edges based on the upper bandwidth limits of the ports at which the logical edges connect with the logical units; and providing the logical edge bandwidths and the timing groups of the logical edges as a cost estimation of implementing the operation unit graph on the reconfigurable processor. 